Traditional module-based memory systems are configured in a multi-drop topology in which multiple memory modules are electrically connected to the same set of signaling wires. Unfortunately, multi-drop topologies suffer from limitations in signaling speeds due to reflections from each of the transmission line stubs created by the module interconnections, as well as the increasing capacitive load as each module is added to the system.
Point-to-point signaling topologies generally enable higher signaling rates than multi-drop arrangements and are increasingly employed between memory controller and memory modules in high-performance memory systems. Capacity-expansion (i.e., adding memory modules) in such memory systems is a challenge, however, as each added memory module typically requires an additional dedicated set of point-to-point links, which are a resource proliferation that sets a practical limit on the number of supportable memory modules.
In some cases (e.g., with fully-buffered dual inline memory-modules (FB-DIMMs)), each module is daisy-chained to the next in order to maintain point-to-point signaling. In these arrangements, data is received on a module from one point-to-point link and then repeated to the next module on the chain through another point-to-point link. In this manner, the point-to-point signaling is maintained without a large quantity of signaling links at the memory controller. However, an expense is incurred in the form of much higher latency, which is a performance penalty that worsens with each module added to the system due to the increasing number of “hops” required to reach the furthest memory module.
In newly developed dynamic point-to-point systems, storage-capacity upgrades are enabled without undue proliferation of signaling links by permitting a memory controller to connect to either i) a single memory module via an N-bit wide point-to-point signaling path, or ii) multiple (M) memory modules via respective N/M-bit wide point-to-point signaling paths. As an example of this approach, an N-bit wide point-to-point signaling path initially dedicated to a single memory module may be subdivided into multiple smaller point-to-point signaling paths as memory modules are added, with each of the smaller paths dedicated to a respective memory module and with the individual data I/O width for each memory device on a given module being configured to have an effective width according to the number of point-to-point links allocated to the module. For example, in a single module configuration, N signaling links may be distributed to X memory devices on the module with the interface width for each memory set to N/X. When that same system is expanded to support two memory modules (i.e., M=2), N/2 signaling links are dedicated to each memory module, with the interface width for each memory device set to (N/2)/X, or half the width of the single-module configuration.
Unfortunately, while specialized memory devices having such selectable interface widths have been developed, more prevalent conventional memory devices have fixed widths and thus are generally limited to use in conventional multi-drop memory systems or point-to-point systems that do not have dynamic point-to-point expansibility.